Communications is involved with the transfer of data. Data which is in a digital format often needs to be manipulated to achieve effective communication. One interface for data is the System Packet Interface (SPI) which has various levels. For example, SPI Level 4 (SPI4, or SPI-4), is a system packet interface for packet and cell transfer between a physical layer (PHY) device and a Link layer device. SPI-4 is capable of handling aggregate bandwidths of OC-192 ATM and Packet over SONET/SDH (POS), as well as 10 Gb/s Ethernet applications.
As originally defined by the Optical Internetworking Forum (OIF), the SPI interface resides between the PHY device and remaining SONET/SDH system and separates the synchronous PHY layer from the asynchronous packet-based processing performed by the higher layers. SPI-4 was originally conceived to perform at 10 G to support the aggregate bandwidth requirements of ATM and POS applications. SPI-4 has become a ubiquitous standard for multi-protocol communications devices operating at 10 G bandwidth, including Gigabit Ethernet and 10 Gigabit Ethernet PHYs, switch fabric interface circuits (FICs), NPUs, security processors, storage processors, traffic managers, mappers, framers, MACs and PHYs. Thus, SPI is a popular interface, however because of the high bandwidths, difficult interfaces, packet delays, and overflows exist. This presents a problem.